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© All Rights Reserved. ApplyBlast.com
accelercomm
The Senior Verification Engineer is responsible for the complete UVM verification of Accelercomm IP, ensuring RTL implementations meet functional, performance, and quality requirements before FPGA deployment and ASIC tape-out. This role involves developing verification plans, creating SystemVerilog/UVM environments, and executing directed and constrained-random verification. The position also includes supporting subsystem integration, contributing to automation workflows, and mentoring junior colleagues.
Headquarters
Southampton, England, United Kingdom
Company Size
51-200 employees
Founded
2016
AccelerComm provides high-performance physical layer IP for 5G and beyond, focused on satellite, terrestrial, and hybrid networks. Its solutions include AX-RG regenerative NTN, AX-TP transparent/hybrid NTN, and embedded LDPC FEC IP, all designed to maximize network performance and efficiency. The company emphasizes substantial data-per-watt advantages over software-only approaches to enable energy-efficient, scalable networks. Overall, AccelerComm offers proven PHY IP that underpins next-generation communications for operators and equipment providers.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for accelercomm.
accelercomm didn’t post a salary, so this is our estimate from similar listings.