SerDes & High-Speed PHY Validation Engineer

This role involves validating and characterizing advanced Ethernet SerDes technologies, including 112G PAM4 and next-generation 224G PHY architectures, to ensure robust high-speed communication solutions for cloud, AI, and data center applications. The engineer will perform high-speed measurements, debug signal integrity challenges, and drive standards compliance while collaborating with cross-functional design and system teams. The position offers hands-on lab work with industry-leading test platforms and opportunities to contribute to automation and silicon bring-up activities.