Senior SerDes & High-Speed PHY Validation Engineer

This role involves leading the validation and characterization of advanced Ethernet SerDes technologies for next-generation high-speed connectivity solutions in cloud, AI, and data center networking systems. The engineer will drive complex technical investigations from first silicon bring-up through compliance and product readiness, working at the intersection of silicon design, signal integrity, and system engineering. The position requires deep signal integrity knowledge, hands-on lab ownership, and automation development to solve challenging high-speed design and validation problems.