SoC Physical Design Intern

The SoC Physical Design Intern on the HBM team supports the implementation of advanced High Bandwidth Memory SoC designs, gaining hands-on experience with physical design methodologies, timing analysis, and automation. The role involves collaborating with multi-functional engineering teams to optimize design blocks and develop innovative solutions for next-generation memory products. This position contributes to delivering high-performance, power-efficient silicon for AI and high-performance computing applications.