Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

This role involves developing and validating timing constraints for intricate System-on-Chip (SoC) designs within Marvell's high-speed semiconductor photonic fabric team. The engineer will collaborate with architecture, RTL, and physical design teams to ensure timing signoff, optimize budgets, and automate STA processes using industry-standard tools. Expertise in advanced technology nodes and static timing analysis methodologies is essential to achieve deterministic timing closure.