SoC Physical Verification Engineer, HBM

This role serves as a key technical contributor within the Heterogeneous Integration Group, responsible for defining and driving sign-off quality physical verification flows for next-generation HBM logic die and memory-centric SoCs. The position requires collaboration across physical design, EDA tool teams, and foundry interfaces to deliver tape-out-ready silicon under aggressive schedule and quality constraints. The engineer will ensure design integrity from layout through first silicon by managing full-chip verification and reliability checks.