Senior Full Chip Layout And Physical Verification Cad Engineer Israel Yokneam

NVIDIA is seeking a Physical Design Engineer to develop full-chip physical design methodologies and verification flows for high-speed networking chips and SOCs. The role involves collaborating with layout owners and project managers to ensure high-quality convergence, debugging verification flows, and creating unique solutions for advanced physical design problems. Candidates will utilize EDA tools and scripting languages to support tapeout activities and drive innovation in chip implementation.