Sr. Staff Engineer, ASIC Physical Design

Ayar Labs is seeking a Sr. Staff Engineer for ASIC Physical Design to lead the implementation of complex SoCs integrating high-speed digital and custom blocks in leading-edge process nodes. The role involves end-to-end responsibility for synthesis, place-and-route, timing closure, and physical verification of mixed-signal designs. This position requires driving design methodologies and coordinating activities across multiple designers to support next-generation AI scale-up architectures.