taiwansemiP1
This role involves driving the development of next-generation SRAM compilers and custom memory architectures within the San Jose Design R&D team. The engineer will collaborate with architecture teams to deliver high-impact silicon solutions that influence customer SoCs while operating on a hybrid schedule. The position requires expertise in advanced process nodes, EDA tools, and compiler verification to ensure robust, silicon-proven deliverables.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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and employee contacts for taiwansemiP1.
5% above the average for this role