STA Engineer

This role involves owning full-chip Static Timing Analysis (STA) signoff across all PVT corners and operational modes, driving timing closure at the chip level, and resolving timing violations. The position requires defining and validating SDC constraints, ensuring proper timing budgeting, and leading signoff methodologies using industry-standard tools. The engineer will also implement MCMM flows, perform SI-aware analysis, and drive timing ECOs to achieve zero or near-zero violations at tapeout.