STA Engineer

This role involves owning full-chip Static Timing Analysis (STA) signoff across all PVT corners and operational modes, driving chip-level timing closure for setup, hold, and noise. The position requires defining and validating SDC constraints, leading signoff methodologies with tools like Synopsys PrimeTime and Cadence Tempus, and performing deep analysis on critical paths and timing violations. The engineer will implement MCMM flows, SI-aware analysis, and ECO strategies to ensure clean signoff with zero or near-zero violations at tapeout.