Staff Design Verification Engineer, UAL and PCIe Subsystems

As a Senior Verification Engineer at Marvell, you will develop functional verification environments, reference models, and bus-functional monitors for high-speed data transfer chips. The role involves creating detailed test plans using random techniques, debugging failures, and architecting tools for multi-core System on Chips (SoCs). You will collaborate with designers to ensure specifications are met for major telecom and automotive customers.