Subsystem/SoC Level Verification Engineer

This role is for a Senior Verification Engineer specializing in Ethernet Subsystem and SoC-level functional verification with 12-15 years of experience. The position requires deep expertise in creating verification environments using System Verilog and UVM, along with developing Block Finite Machines (BFMs) and monitors for complex system architectures. Candidates must be proficient in gate-level simulations, constrained random verification, and debugging test failures using industry-standard CAD tools.