Staff Hardware Engineer in Design Verification

The Staff Hardware Engineer in Design Verification will own the verification strategy and execution for complex out-of-order processor and cache/memory subsystems. This role involves defining methodology, leading testplan creation, and driving verification of speculative execution, memory ordering, and coherence features from architecture through tape-out. The position requires strong expertise in System Verilog, UVM, and OOO CPU micro-architecture to ensure comprehensive coverage and quality.