SiFive
This role leads the verification and optimization of SiFive's RISC-V Low Power Profiles, including UPF, to drive quality closure at CPU and block levels. The position involves collaborating with microarchitecture and RTL design teams to optimize complex power flows while providing technical mentorship to junior members. Candidates will actively participate in test planning and execution for new architecture and design features.
Headquarters
Santa Clara, California, United States
Company Size
501-1000 employees
Founded
2015
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for SiFive.
SiFive didn’t post a salary, so this is our estimate from similar listings.
15% below the average for this role
SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion
Jan 15, 2026
Risc V Cpu Design Sr Engineer Bangalore Karnataka India
Qualcomm Incorporated
CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)
GlobalFoundries
Staff Engineer AI/ML
GlobalFoundries
Risc V Cpu Design Sr Staff Engineer Bangalore Karnataka India
Qualcomm Incorporated
AI CPU Design Engineer
GlobalFoundries
CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)
GlobalFoundries