Staff/ Sr Staff/Principal Engineer, STA

Renesas is seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis to own RTL-to-Gate conversion and ensure final timing closure. The role focuses on optimizing physical-aware synthesis flows and managing constraint development to deliver chips with maximum performance at the lowest power and area. This position requires extensive experience in multi-mode and multi-corner timing closure, low-power implementation, and scripting to automate design flows.