Staff/Sr. Staff/Principal STA/Synthesis Engineer

The Staff/Sr. Staff/Principal STA/Synthesis Engineer at Velaura AI owns RTL-to-gate synthesis, static timing analysis, and timing closure for next-generation AI and high-performance computing silicon. This role drives implementation quality, timing convergence, and power optimization for complex compute, CPU, VPU, and low-power cores targeting advanced process technologies. The engineer collaborates with cross-functional teams to achieve aggressive Performance, Power, Area, and Cost targets while influencing synthesis strategy and implementation best practices.