Staff/Sr. Staff Physical Verification Engineer

The Staff/Sr. Staff Physical Verification Engineer at Velaura AI owns block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. This hands-on role involves driving physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies. The position requires deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification to achieve first-time-right silicon.