Static Timing Analysis (STA) Engineer

The Static Timing Analysis (STA) Engineer will own chip-level timing sign-off for next-generation die within the Heterogeneous Integration Group, ensuring timing integrity and driving closure across all modes and corners. This hands-on senior technical role focuses on STA ownership, constraint authoring, methodology development, and pre- and post-silicon timing correlation. The engineer will collaborate with cross-functional teams to deliver low-power, high-density memory solutions for AI and ML applications.