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Tech Lead, Asic DV at Astera Labs - ApplyBlast

Tech Lead, Asic DV

Astera Labs

1 day ago

4.3 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Tech Lead for Design Verification to develop and execute verification plans for complex SoC/silicon products. The role involves collaborating with RTL designers, writing test sequences, and utilizing coding and protocol expertise to ensure functional verification. This position requires a strong background in Electrical or Computer Engineering and experience with industry-standard simulators and regression systems.

Responsibilities

Develop and execute block-level and system-level verification plans
Write and execute test sequences using UVM to generate stimuli
Collaborate with RTL designers to debug failures and refine verification processes

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.