Top Level Integration Engineer

The Top Level Integration Engineer is responsible for integrating individual chip blocks into a complete chip layout, managing bump and RDL routing, and driving full-chip physical verification through tapeout. This role requires hands-on experience with GDS/OASIS integration, DRC/LVS signoff, and EDA tools like Cadence Innovus and Siemens Calibre. The engineer will independently own the full-chip integration process from assembly through final deliverables.