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© All Rights Reserved. ApplyBlast.com
JPMorganChase
The Ultra Low Latency C++ Lead Software Engineer at JPMorgan Chase designs, builds, and operates market gateway solutions with hardware FPGA acceleration. This role focuses on driving the software development lifecycle with an emphasis on stability, latency optimization, and continuous improvement. The engineer partners with hardware teams to integrate FPGA pipelines with the C++ software stack, ensuring high reliability and operational excellence for trading connectivity and risk management applications.
JPMorgan Chase is a leading global financial services firm that provides a full range of banking, investment banking, asset and wealth management, and payments and treasury services to consumers, businesses, governments, and institutions. Its consumer business operates under the Chase brand, offering retail banking, credit cards, mortgages and auto loans, while J.P. Morgan delivers corporate & investment banking, markets, securities services and asset management. Headquartered in New York, the firm combines scale, technology and risk management to serve clients worldwide. It is one of the largest banks by assets and is widely recognized for its capital markets expertise and integrated financial solutions.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for JPMorganChase.
JPMorganChase didn’t post a salary, so this is our estimate from similar listings.
19% below the average for this role
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