JPMC
The Ultra Low Latency C++ Lead Software Engineer at JPMorgan Chase designs, builds, and operates market gateway solutions with hardware FPGA acceleration for the Electronic Trading Technology team. This role focuses on driving the software development lifecycle to ensure stability, latency optimization, and continuous improvement while integrating FPGA pipelines with the C++ software stack. The position directly impacts trading connectivity and risk management applications used by clients and internal businesses.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for JPMC.
JPMC didn’t post a salary, so this is our estimate from similar listings.
27% below the average for this role
Ultra Low Latency C++ Lead Software Engineer
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Ultra Low Latency C++ Lead Software Engineer
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Ultra Low Latency C++ Lead Software Engineer
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Ultra Low Latency C++ Lead Software Engineer
JPMorganChase