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© All Rights Reserved. ApplyBlast.com
d-Matrix
The role involves hands‑on transistor‑level analog design of the clocking subsystem for a high‑speed SerDes IO chiplet, covering PLL, DLL, phase interpolator, clock distribution, and CDR loop, from specification through silicon bring‑up and characterization. The engineer will collaborate with datapath, DSP, digital, and firmware teams to meet timing and jitter budgets.
Headquarters
Santa Clara, California, United States
Company Size
51-200 employees
Founded
2019
d-Matrix is building ultra-low latency, batched inference for Generative AI through an efficient memory–compute integration—the world’s first of its kind. By unifying memory and compute, their solution accelerates large language models and other generative workloads with high throughput and lower power consumption. The platform aims to make Generative AI inference blazing fast, sustainable, and commercially viable at scale for enterprises. Positioned as a memory-centric AI acceleration pioneer, d-Matrix enables faster, more cost-effective AI service deployments.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for d-Matrix.
16% above the average for this role
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