Celero Inc
The role involves architecting and designing advanced PLL building blocks and clocking circuits for next-generation optical transceivers, high-speed SerDes, and ADC/DAC systems. The engineer will work on transistor-level design, simulation, layout verification, and lab bring-up in advanced CMOS nodes.
Celero Inc.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Celero Inc.
15% above the average for this role