Celero Inc
Celero Communications is seeking an ASIC Design Engineer to develop high-performance digital circuits and mixed-signal ASIC blocks for optical communication systems. The role involves designing, implementing, and optimizing digital, DSP, and high‑speed SerDes functionality, collaborating with cross‑functional teams, and contributing from architecture through silicon validation.
Celero Inc.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Celero Inc.
15% above the average for this role
Principal Engineer, Analog/Mixed Signal Modelling and Verification
8a7883c66a3387ef016a468ba9d104e6
Senior Engineer, Analog/Mixed Signal Modelling and Verification
8a7883c66a3387ef016a468ba9d104e6
Principal Design Verification Engineer- SerDes/PHY IP
Astera Labs
Sr. Staff Engineer, Analog/Mixed Signal Modelling and Verification
8a7883c66a3387ef016a468ba9d104e6
ASIC Engineering Analog Design Leader
Cisco Systems, Inc.
Analog Mixed-Signal Lead Design Engineer (T3) – SerDes
Cadence