ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

The role involves leading Design-for-Test (DFT) implementation for complex ASICs within the Silicon One development organization, collaborating with front-end RTL and backend physical design teams to drive testability requirements early in the design cycle. The position requires expertise in DFT IP development, test logic integration, and post-silicon validation to support ATE, in-system test, and debug needs. The successful candidate will contribute to crafting innovative hardware DFT strategies for next-generation networking chips.