ASIC DFT Engineer - 4 to 8 yrs

The ASIC DFT Engineer role involves implementing Hardware Design-for-Test features to support ATE, in-system test, debug, and diagnostics needs for Cisco's core networking hardware. The position requires developing innovative DFT IP and collaborating with multi-functional teams to integrate testability features into full chip designs. This role focuses on enabling the integration and validation of test logic across implementation and post-silicon validation flows.