ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore

The ASIC Implementation Technical Lead focuses on Design-for-Test within the Silicon One development organization, collaborating with front-end and backend teams to drive DFT requirements and quality processes. This role involves leading the definition and architecture of high-performance ASICs, overseeing reusable code, and managing the DFT flow from conception through post-silicon validation. The position requires expertise in JTAG protocols, ATPG, and EDA tools to ensure successful chip design and verification.