ASIC Engineer || Physical Design, CAD Methodology || STA Setup, Convergence Methodology || Exp 4+ years

Join the Cisco SiliconOne team in Bangalore to create next-generation networking chips using advanced process nodes. This role involves driving the backend process through the entire RTL 2 GDS Implementation flow, including hierarchical floor planning, place & route, and timing closure. The position focuses on performance and die size optimization while ensuring physical convergence and power integrity.