Cisco Systems, Inc.
The ASIC Engineer role involves creating next-generation networking chips in advanced process nodes, driving the backend process through the entire RTL 2 GDS Implementation flow. This includes hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks, with a focus on performance and die size optimization. The position is part of the Cisco SiliconOne team, offering exposure to various aspects of systems and applications.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Cisco Systems, Inc..
Cisco Systems, Inc. didn’t post a salary, so this is our estimate from similar listings.
ASIC Engineer || Physical Design, CAD Methodology || STA Setup, Convergence Methodology || Exp 4+ years
Cisco
Physical Design Intern
marvellsemiconductor.com
Senior ASIC Timing Engineer, DFT
NVIDIA
Implementation Timing Sta Design Engineer San Diego California United States Of America
Qualcomm Incorporated
Director, STA & PD Closure
Altera
ASIC-PD Engineer
Coherent