ASIC Verification Engineer

The ASIC Verification Engineer at HPE develops and maintains comprehensive verification environments using SystemVerilog and UVM methodologies for block, subsystem, and full-chip designs. Responsibilities include creating test suites, executing simulations on industry-standard tools, and collaborating with RTL designers and software teams to resolve design issues before tape-out. This role focuses on driving functional verification, analyzing code coverage, and enhancing productivity through automation scripting.