Principal ASIC Design Verification Engineer

K2 is seeking a Principal ASIC Design Verification Engineer to verify the functionality and robustness of their custom silicon designs for high-power satellite platforms. The role involves defining verification methodologies, building SystemVerilog/UVM testbenches, and collaborating with architecture and RTL design teams to ensure first-generation silicon success. Candidates will drive test strategies, manage simulation farms, and support silicon bring-up across block, subsystem, and full-chip environments.