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DDR PHY IP Front End Design at Cadence - ApplyBlast

DDR PHY IP Front End Design

Cadence

12 days ago

4.0 on Glassdoor

Shanghai, China

Onsite

Full Time

Senior

0 applicants

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About this role

The Cadence DDR PHY IP Front End Design team is seeking a professional to develop firmware for DDR5 PHY using microcontrollers. The role involves collaborating with hardware designers and memory subsystem architects to derive and implement training algorithms. Additionally, the position requires working with the verification team on firmware-hardware co-verification plans and debugging firmware in simulations and on silicon bring-up boards.

Responsibilities

Develop firmware for DDR5 PHY using microcontrollers
Collaborate with hardware designers to derive training algorithms
Debug firmware in RTL based hardware simulations

Skills

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.