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© All Rights Reserved. ApplyBlast.com
Altera
The role serves as the technical owner and team leader for Static Timing Analysis flows and timing modeling methodology across Altera's ASIC, Custom, and Semi-Custom IP designs. The position involves developing and deploying production-grade design automation flows, collaborating with cross-functional teams, and driving engagements with major EDA vendors. The ideal candidate will leverage deep expertise in timing analysis, characterization, and automation to support design teams through tape-out and sign-off.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
31% above the average for this role