Principal Static Timing Analysis Engineer
Silicon Labs(2 days ago)
About this role
The Principal Static Timing Analysis Engineer at Silicon Labs focuses on developing timing constraints and facilitating timing closure for low power Wireless SoCs and IP systems. The role involves collaborating with global teams to analyze timing reports, improve timing analysis flows, and support the development of advanced edge connectivity applications.
Required Skills
- Verilog
- System Verilog
- Tcl
- Python
- Scripting
- Timing Closure
- Static Timing Analysis
- Power Gating
- AI Tools
- Synthesis
Qualifications
- BS in Electrical or Computer Engineering
- 15+ years in Industry
About Silicon Labs
silabs.comSilicon Labs makes silicon, software and solutions for a more connected world.
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