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Design Verification Engineer, New Grad at SambaNova Systems - ApplyBlast

Design Verification Engineer, New Grad

SambaNova Systems

3 days ago

3.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Junior

0 applicants

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About this role

As a new grad Design Verification Engineer at SambaNova, you will write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You will run regressions, debug simulation failures, and collaborate with RTL designers to find and fix bugs before tape-out. The role focuses on verifying the RDU, SambaNova's chip for AI workloads, ensuring robust chip-level control and initialization.

Responsibilities

Write and execute verification plans for chip-level control and initialization features
Build SystemVerilog and UVM testbench components including sequences and checkers
Debug simulation and regression failures with RTL designers to find and fix bugs

Skills

Qualifications

B.S. in Electrical EngineeringB.S. in Computer EngineeringB.S. in Computer Science

About SambaNova Systems

sambanova.ai

Headquarters

Palo Alto, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

SambaNova is an AI systems company that delivers an integrated hardware-and-software platform positioned as a high-performance alternative to GPUs for enterprise and agentic AI. The platform emphasizes the fastest AI inference, streamlined fine-tuning, and scalable deployment options. SambaCloud offers the company’s solutions as a cloud-hosted on-ramp for customers to accelerate production AI workloads.