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© All Rights Reserved. ApplyBlast.com
Astera Labs
Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP, ensuring first-pass silicon success for next-generation AI systems. This hands-on role involves partnering with analog and digital teams to verify multi-Gbps SerDes blocks for advanced AI platforms. The position requires architecting verification environments, driving coverage closure, and collaborating across cross-functional teams to support rack-scale AI infrastructure.
Headquarters
Santa Clara, California, United States
Company Size
201-500 employees
Founded
2017
Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Astera Labs.
21% above the average for this role
Why Astera Labs Shares Are Surging On Wednesday - Astera Labs (NASDAQ:ALAB)
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