ApplyBlast uses AI to match you with the right jobs, tailor your resume and cover letter, and apply automatically so you can land your dream job faster.
© All Rights Reserved. ApplyBlast.com
ApplyBlast uses AI to match you with the right jobs, tailor your resume and cover letter, and apply automatically so you can land your dream job faster.
© All Rights Reserved. ApplyBlast.com
Silvaco
This role involves developing test plans and architecting system-level verification environments using UVM and SystemVerilog. The engineer will create constrained-random stimulus, scoreboards, and coverage models while contributing to regression infrastructure and FPGA-based prototyping. Key duties include executing simulations, analyzing coverage holes, and automating the design/verification process.
Headquarters
Santa Clara, California, United States
Company Size
201-500 employees
Founded
1984
Silvaco is a provider of EDA software and semiconductor IP focused on process and device development for advanced semiconductors, including power ICs, displays, and memory. Its products span TCAD process/device simulation, circuit simulation and compact modeling, and reusable IP blocks used by design houses, foundries, and fabs. Silvaco’s tools enable engineers to optimize fabrication processes, device characteristics, and circuit performance across advanced and specialty technologies. The company markets itself as a global partner for accurate simulation, modeling, and IP to accelerate semiconductor development.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Silvaco.
Silvaco didn’t post a salary, so this is our estimate from similar listings.
Right around the average for this role