taiwansemiP1
This role focuses on the design and implementation of high-speed interfaces for SerDes or chiplet interconnects, emphasizing electrical performance optimization and reliability. The position involves 2.5D/3DIC channel modeling and requires a deep understanding of high-speed interface architecture from theory through silicon validation. Candidates must have a Master's or PhD in Electrical Engineering and over three years of relevant industry experience.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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taiwansemiP1 didn’t post a salary, so this is our estimate from similar listings.
Right around the average for this role
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