Lead Debug/Trace/Profiling Design Engineer
SiFive(2 months ago)
About this role
SiFive is hiring a technical lead to design industry-leading debug, trace and profiling IP for RISC-V processor subsystems. The role focuses on building configurable RTL generators using Chisel/Scala and integrating them into SiFive’s IP portfolio across product lines. The position also involves engagement with customers, partners, tools vendors and the RISC-V community to shape future debug and profiling solutions.
Required Skills
- Debug Architecture
- Trace Architecture
- Profiling
- Chisel
- Scala
- RTL Design
- Verilog
- SystemVerilog
- VHDL
- JTAG
+5 more
Qualifications
- MS in EE/CE/CS
- PhD in EE/CE/CS
About SiFive
sifive.comAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
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