Lead Debug/Trace/Profiling Design Engineer

SiFive is hiring a technical lead to design industry-leading debug, trace and profiling IP for RISC-V processor subsystems. The role focuses on building configurable RTL generators using Chisel/Scala and integrating them into SiFive’s IP portfolio across product lines. The position also involves engagement with customers, partners, tools vendors and the RISC-V community to shape future debug and profiling solutions.