Lead Engineer - CAD Physical Verification

The Lead Engineer - CAD Physical Verification role supports design and layout teams during chip development by debugging physical verification queries and developing rule decks for DRC, Antenna, Dummy fill, LVS, and extraction. The position involves collaborating with cross-functional teams to gather specifications, automating verification flows, and evaluating new tools to improve quality and performance. This role requires strong expertise in physical verification methodologies and scripting to optimize chip design processes.