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Lead Logic Design Engineer at Astera Labs - ApplyBlast

Lead Logic Design Engineer

Astera Labs

1 month ago

4.3 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Lead Logic Design Engineer with 6-10 years of experience to lead the development of complex connectivity IPs and subsystems. The role involves technical ownership across architecture, microarchitecture, RTL implementation, and silicon bring-up for high-performance hardware components. The successful candidate will drive performance optimization, collaborate with verification and integration teams, and mentor senior engineers.

Responsibilities

Lead RTL and microarchitecture development for complex connectivity IP
Translate specifications into robust hardware architecture and scalable logic
Drive performance optimization and support post-silicon debug

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.