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Principal Digital Design Engineer at Astera Labs - ApplyBlast

Principal Digital Design Engineer

Astera Labs

6 days ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal Digital Design Engineer to lead the micro-architecture and front-end circuit design for high-performance network controllers. The role involves developing RTL, managing synthesis and IP integration, and overseeing block-level verification for complex SoC and silicon products. This position requires extensive experience with high-speed communication protocols and digital design tools to drive designs from architecture to production.

Responsibilities

Develop micro-architecture and front-end circuit design for high performance network controllers
Drive complex designs from architecture to GDS and manage block-level verification
Perform silicon bring-up and debug for small-geometry CMOS products

Skills

Qualifications

Bachelor's degree in EEMaster's degree

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.