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NoC Design Verification Engineer at SiFive - ApplyBlast

NoC Design Verification Engineer

SiFive

4 months ago

3.9 on Glassdoor

Ahmedabad, India

Onsite

Full Time

Senior

0 applicants

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About this role

The Design Verification Engineer develops and executes verification plans for Network on Chip (NoC) and coherent interconnect IP at SiFive. Responsibilities include building UVM/SystemVerilog environments, creating assertions and coverage models, and collaborating with design teams to debug simulation failures for large SoC interconnects.

Responsibilities

Develop and execute verification plans for NoC and interconnect subsystems
Build UVM and SystemVerilog-based verification environments and testbenches
Create assertions, checkers, and functional coverage models aligned with specifications
Debug simulation failures and isolate root causes with RTL design teams
Verify multiple NoC configurations, topologies, and protocol interactions

Skills

Qualifications

BS in Electrical EngineeringBS in Computer EngineeringMS in Electrical EngineeringMS in Computer Engineering

About SiFive

sifive.com

Headquarters

Santa Clara, California, United States

Company Size

501-1000 employees

Founded

2015

View Profile

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.