Altera
This role focuses on the physical design implementation of custom IP and SoC designs, guiding the process from RTL to GDS to ensure manufacturing readiness. The position involves conducting comprehensive physical design flows, including synthesis, place and route, and static timing analysis, while performing verification and signoff tasks. The engineer analyzes results to fix violations and optimizes designs to enhance product-level parameters such as power, frequency, and area.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.