Sr. Physical Design Engineer

The Sr. Physical Design Engineer leads the complete physical implementation flow from RTL to GDS, encompassing synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, and signoff. This role involves block-level floorplanning, customized clock tree structures, and implementing engineering change orders for timing closure. The position requires expertise in signal EM/Noise and power IR/EM analysis, as well as physical verification signoff for tapeout production chips.