Physical Design Implementation and STA Lead

Altera is seeking a Physical Design Implementation & Static Timing Analysis (STA) Lead to drive high-quality physical implementation and timing closure for next-generation FPGA SoCs. This highly technical individual contributor role involves leading block-level implementation activities, providing technical guidance to engineers, and evaluating emerging ML/AI-assisted physical design technologies. The position requires deep expertise in synthesis, floorplanning, place-and-route, and static timing analysis to achieve timing, power, and area goals.