Principal Digital Design Engineer (AI Fabric)
Astera Labs(1 month ago)
About this role
The Principal Digital Design Engineer will architect and implement next-generation digital designs for high-performance connectivity SoCs, owning complex blocks from micro-architecture through silicon bring-up. The role involves driving RTL implementation, collaborating across verification, PD, DFT and post-silicon teams, and ensuring designs reach production in a fast-paced environment. The position expects leadership in improving silicon development processes and mentoring junior engineers.
Required Skills
- Micro-Architecture
- RTL Coding
- Functional Simulation
- Synthesis
- Timing Closure
- Gate-Level Simulation
- DFT
- Silicon Bring-Up
- Failure Analysis
- Debug
+15 more
Qualifications
- BS in Electrical Engineering
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.