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Principal Digital Digital RTL Engineer at Astera Labs - ApplyBlast

Principal Digital Digital RTL Engineer

Astera Labs

2 months ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

The Principal Engineer on the Analog/Mixed-Signal (AMS) Design team will architect and deliver high‑performance analog building blocks for Astera Labs' connectivity silicon, overseeing designs from specification through silicon bring‑up. This hands‑on technical leadership role involves setting technical direction, mentoring engineers, and collaborating across digital, system, product, and packaging teams to enable rack‑scale AI infrastructure.

Responsibilities

Architect and design high‑speed analog/mixed‑signal circuits
Lead verification, silicon bring‑up, and debugging across PVT corners
Provide technical direction and mentor engineers across the team

Skills

Qualifications

MS in Electrical EngineeringPhD in Electrical Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.